Continuously variable switched capacitor dc-dc voltage converter

ABSTRACT

A voltage converter is switched among two or more modes to produce an output voltage matching a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. The output voltage is compared with the reference voltage to determine whether to adjust the mode.

CROSS-REFERENCE TO RELATED APPLICATION

The benefit of the filing date of U.S. Provisional Patent ApplicationSer. No. 61/265,454, filed Dec. 1, 2009, entitled “Continuously VariableSwitched Capacitor DC-DC Supply,” is hereby claimed, and thespecification thereof is incorporated herein in its entirety by thisreference. U.S. patent application Ser. No. ______, filed ______,entitled “VOLTAGE CONVERSION METHOD IN A CONTINUOUSLY VARIABLE SWITCHEDCAPACITOR DC-DC VOLTAGE CONVERTER,” is related.

BACKGROUND

One type of device that converts one DC voltage level to another iscommonly known as a DC-to-DC converter (or “DC-DC” converter). DC-DCconverters are commonly included in battery-operated devices such asmobile telephones, laptop computers, etc., in which the varioussubsystems of the device require several discrete voltage levels. Insome types of devices, such as a mobile telephone that operates in anumber of different modes, it is especially desirable to supply certainelements, such as power amplifiers, with a supply voltage at the mostefficient level for the mode of operation, rather than waste power andaccordingly drain the battery prematurely. In such devices, it isdesirable to employ a DC-DC converter that can generate a greater numberof discrete voltage levels.

Several types of DC-DC converters are known, including switched-modeDC-DC converters and DC-DC converters that employ pulse-width modulation(PWM). Switched-mode DC-DC converters convert one DC voltage level toanother by storing the input energy momentarily in inductors orcapacitors and then releasing that energy to the output at a differentvoltage. The switching circuitry thus continuously switches between twostates or phases: a first state in which a network of inductors orcapacitors is charging, and a second state in which the network isdischarging. The switching circuitry can be configured to generate anoutput voltage that is a fixed fraction of the battery voltage, such asone-third, one-half, two-thirds, etc., where a mode selection signal isprovided as an input to the switching circuitry to control which of thefractions is to be employed. Different configurations of the network ofinductors or capacitors can be selected by manipulating switches in thenetwork using the mode selection signal.

The number of discrete output voltages that a switched-mode DC-DCconverter can generate is related to the number of inductors orcapacitors. In a portable, handheld device such as a mobile telephone itis desirable to minimize size and weight. A DC-DC converter having alarge number of inductors or capacitors is not conducive to minimizingthe size and weight of a mobile telephone. A PWM-based DC-DC convertercan generate a larger number of discrete voltages than a switched-modeDC-DC converter without employing significantly more inductors,capacitors or other elements. However, a PWM-based DC-DC converter cangenerate a large spectrum of spurious output signals that can adverselyaffect the operation of a mobile telephone or other frequency-sensitivedevice. Filters having large capacitances or inductances can be includedin a PWM-based DC-DC converter to minimize these spurious signals, butlarge filter capacitors or inductors are undesirable for the samereasons described above.

SUMMARY

Embodiments of the invention relate to a switching voltage converterthat can produce an output signal of not only any of a number ofdiscrete voltage levels but also of intermediate values between thediscrete voltage levels, by switching between two or more selectablemodes, each corresponding to one of the discrete voltage levels. In anexemplary embodiment, the voltage converter is a switched-capacitorvoltage converter having a two or more capacitors, a switch matrix,comparator logic, and control logic. A reference signal is input to thecomparator logic, which also receives the output signal as feedback. Ineach mode, the switch matrix interconnects the capacitors in a differentconfiguration. Each mode or mode configuration has two phaseconfigurations: one in which the capacitor circuit is charged andanother in which the capacitor circuit is discharged. The switch matrixswitches between the two phase configurations of a selected modeconfiguration in response to a clock signal. As a result of thisswitching, the voltage converter produces an output signal having avoltage that corresponds to a selected mode configuration. Byalternately switching between two of the modes, the voltage convertercan produce an output voltage having a level that corresponds to thereference signal voltage in an instance in which the reference signalvoltage lies between two of the discrete voltage levels corresponding tothose modes.

In the exemplary embodiment, the comparator logic compares the outputsignal with the reference signal and produces a direction comparisonsignal indicating which of the output signal and the reference signal isgreater in magnitude than the other. The comparison signal thusindicates whether the control logic is to cause the output signalvoltage to increase or decrease to match the reference signal.

In the exemplary embodiment, the control logic uses one or more signalsfrom the comparator logic, including the direction comparison signal, toselect the mode. If the direction comparison signal indicates that thereference signal is greater than the output signal, the control logiccan switch the mode to one that corresponds to an output signal voltagethat is greater than the reference signal. Changing the mode in thismanner causes the output signal voltage to increase. However, if thedirection comparison signal indicates that the output signal is greaterthan the reference signal, the control logic can switch the mode to onethat corresponds to an output signal voltage less than the referencesignal. Changing the mode in this manner causes the output signalvoltage to decrease.

Other systems, methods, features, and advantages of the invention willbe or become apparent to one with skill in the art upon examination ofthe following figures and detailed description.

BRIEF DESCRIPTION OF THE FIGURES

The invention can be better understood with reference to the followingfigures. The components within the figures are not necessarily to scale,emphasis instead being placed upon clearly illustrating the principlesof the invention. Moreover, in the figures, like reference numeralsdesignate corresponding parts throughout the different views.

FIG. 1 is a block diagram of a voltage converter in accordance with anexemplary embodiment of the present invention.

FIG. 2A is a circuit diagram illustrating the switch matrix shown inFIG. 1 in a first phase configuration of a first mode configuration.

FIG. 2B is a circuit diagram similar to FIG. 2A, illustrating the switchmatrix in a second phase configuration of the first mode configuration.

FIG. 3A is a circuit diagram illustrating the switch matrix shown inFIG. 1 in a first phase configuration of a second mode configuration.

FIG. 3B is a circuit diagram similar to FIG. 2A, illustrating the switchmatrix in a second phase configuration of the second mode configuration.

FIG. 4A is a circuit diagram illustrating the switch matrix shown inFIG. 1, illustrating the switch matrix in a first phase configuration ofa variant of the second mode configuration.

FIG. 4B is a circuit diagram similar to FIG. 3B, illustrating the switchmatrix in a second phase configuration of the variant of the second modeconfiguration.

FIG. 5A is a circuit diagram illustrating the switch matrix shown inFIG. 1 in a first phase configuration of a third mode configuration.

FIG. 5B is a circuit diagram similar to FIG. 2A, illustrating the switchmatrix in a second phase configuration of the third mode configuration.

FIG. 6 is a circuit diagram of the comparator circuit shown in FIG. 1.

FIG. 7 is a table illustrating combinational logic of the mode selectionlogic shown in FIG. 1.

FIG. 8 is a circuit diagram illustrating the switch control logic shownin FIG. 1.

FIG. 9 is a timing diagram illustrating an exemplary instance ofoperation of the voltage converter of FIG. 1.

FIG. 10 is a flow diagram illustrating an exemplary method of operationof the voltage converter of FIG. 1.

DETAILED DESCRIPTION

As illustrated in FIG. 1, in an illustrative or exemplary embodiment ofthe invention, a voltage converter 10 includes two capacitors 12 and 14,a switch matrix 16, a comparator circuit 18, and control logic 20. Areference voltage signal (V_REF) is provided to voltage converter 10 asa control input. In the manner described below, voltage converter 10produces an output voltage signal (V_OUT) that corresponds to or tracksthe reference voltage signal. Voltage converter 10 further includes aclock signal generator circuit 22 and associated oscillator 24 that canbe activated by an Enable signal. The Enable signal remains activeduring the operation described below.

Switch matrix 16 can assume one of several mode configurations,described below, in which capacitors 12 and 14 are interconnected indifferent configurations. In each mode configuration, switch matrix 16can assume either a first phase configuration, in which the capacitorcircuit defined by the interconnected capacitors 12 and 14 is charging,or a second phase configuration, in which the capacitor circuit definedby the interconnected capacitors 12 and 14 is discharging. Switch matrix16 provides the output of the capacitor circuit at an output node 26. Inoperation, switch matrix 16 alternately switches between the first andsecond phase configurations in response to the clock signal. Filtercircuitry, such as a capacitor 28, can be connected to output node 26 tofilter the output voltage signal.

As described in further detail below, comparator circuit 18 compares theoutput voltage signal with the reference voltage signal and, inresponse, produces a number of comparison signals 30. Control logic 20includes mode selection logic 32 and switch control logic 34. Modeselection logic 32 receives comparison signals 30 and, in response,produces mode selection signals 36. Switch control logic 34 receivesmode selection signals 36 and, in response, produces switch controlsignals 38.

As illustrated in FIGS. 2A, 2B, 3A, 3B, 4A, 4B, 5A and 5B, switch matrix16 can interconnect capacitors 12 and 14 in several differentconfigurations between a voltage potential (i.e., either the batteryvoltage or ground) and output node 26. Switch matrix 16 includes nineswitches 40, 42, 44, 46, 48, 50, 52, 54 and 56, which are controlled bythe above-referenced switch control signals 38 (S1-S9). Althoughswitches 40-56 are shown schematically in FIGS. 2-5 in the form ofcontrollable, single-pole, single-throw (SPST) switches, they cancomprise any suitable switching devices, such as field-effecttransistors (FETs). For example, each of switches 40 and 50 can comprisea P-type FET (PFET), each of switches 46 and 56 can comprise an N-typeFET (NFET), and each of switches 42, 44, 48, 52 and 54 can comprise aparallel combination of a PFET and an NFET. The control terminal (e.g.,gate) of each FET can receive one of switch control signals 38 (S1-S9).

Although in the exemplary embodiment switch matrix 16 includes nineswitches, which can be arranged as shown, in other embodiments a switchmatrix can include any other number of switches arranged in any othersuitable manner. Similarly, although the exemplary embodiment includestwo capacitors 12 and 14, which switch matrix 16 can interconnect asdescribed below, other embodiments can include more than two capacitors,and a switch matrix can interconnect them in any other suitableconfigurations.

As illustrated in FIGS. 2A-B, in a first configuration, switch matrix 16can interconnect capacitors 12 and 14 in either the first phaseconfiguration shown in FIG. 2A or the second phase configuration shownin FIG. 2B. This first configuration can be referred to herein as the “⅓mode” because operation in this mode is intended to result in an outputvoltage signal (V_OUT) at output node 26 having a voltage level that isnominally or on average about one-third of the battery voltage (V_BATT).

As shown in FIG. 2A, in the first phase configuration of the ⅓ mode,switches 40, 48, 44, 50 and 54 are open, and switches 42, 46, 52 and 56are closed. The combination of the closed states of switches 42 and 46couples capacitor 12 between a ground voltage potential (0 volts) andoutput node 26. The combination of the closed states of switches 52 and56 similarly couples capacitor 14 between the ground potential andoutput node 26 (i.e., in parallel with capacitor 12). Thus, in the firstphase configuration of the ⅓ mode, the capacitor circuit defined bycapacitors 12 and 14 in parallel with each other discharges with respectto output node 26.

As shown in FIG. 2B, in the second phase configuration of the ⅓ mode,switches 42, 44, 46, 50, 52 and 56 are open, and switches 40, 48 and 54are closed. The combination of the closed states of switches 40, 48 and54 couples capacitors 12 and 14 in series between a positive voltagepotential, such as a base reference voltage provided by a battery(V_BATT), and output node 26. Thus, in the second phase configuration ofthe ⅓ mode, the capacitor circuit defined by capacitors 12 and 14 inseries with each other charges with respect to output node 26.

As illustrated in FIGS. 3A-B, in a second configuration, switch matrix16 can interconnect capacitors 12 and 14 in either the first phaseconfiguration shown in FIG. 3A or the second phase configuration shownin FIG. 3B. This second configuration can be referred to herein as the“½A mode” because operation in this mode is intended to result in anoutput voltage signal (V_OUT) at output node 26 having a voltage levelthat is nominally or on average about one-half of the battery voltage(V_BATT). Also, as described below, there is a variant of the ½A mode,referred to as the ½B mode.

As shown in FIG. 3A, in the first phase configuration of the ½A mode,switches 40, 44, 48, 50 and 54 are open, and switches 42, 46, 52 and 56are closed. The combination of the closed states of switches 42 and 46couples capacitor 12 between ground and output node 26. The combinationof the closed states of switches 52 and 56 similarly couples capacitor14 between ground and output node 26 (i.e., in parallel with capacitor12). Thus, in the first phase configuration of the ½A mode, thecapacitor circuit defined by capacitors 12 and 14 in parallel dischargeswith respect to output node 26.

As shown in FIG. 3B, in the second phase configuration of the ½A mode,switches 42, 46, 48, 52 and 56 are open, and switches 40, 44, 50 and 54are closed. The combination of the closed states of switches 40 and 44couples capacitor 12 between the battery voltage and output node 26. Thecombination of the closed states of switches 50 and 54 similarly couplescapacitor 14 between the battery voltage and output node 26 (i.e., inparallel with capacitor 12). Thus, in the second phase configuration ofthe ½A mode, the capacitor circuit defined by capacitors 12 and 14 inparallel with each other charges with respect to output node 26.

The ½B mode variant of the second mode configuration is shown in FIGS.4A-B. The second mode configuration includes both the ½A and ½B modes orsub-modes to minimize the number of switches that change state duringswitching from one mode to another, as described below. Although thesesub-modes are included in the exemplary embodiment, in other embodimentssuch sub-modes need not be included.

As shown in FIG. 4A, in the first phase configuration of the ½B mode,switches 42, 46, 48, 52 and 56 are open, and switches 40, 44, 50 and 54are closed. The combination of the closed states of switches 40 and 44couples capacitor 12 between the battery voltage and output node 26. Thecombination of the closed states of switches 50 and 54 similarly couplescapacitor 14 between the battery voltage and output node 26 (i.e., inparallel with capacitor 12). Thus, in the second phase configuration ofthe ½B mode, the capacitor circuit defined by capacitors 12 and 14 inparallel charge with respect to output node 26.

As shown in FIG. 4B, in the second phase configuration of the ½B mode,switches 40, 44, 48, 50 and 54 are open, and switches 42, 46, 52 and 56are closed. The combination of the closed states of switches 42 and 46couples capacitor 12 between ground and output node 26. The combinationof the closed states of switches 52 and 56 similarly couples capacitor14 between ground and output node 26 (i.e., in parallel with capacitor12). Thus, in the second phase configuration of the ½B mode, thecapacitor circuit defined by capacitors 12 and 14 in parallel with eachother discharges with respect to output node 26.

As illustrated in FIGS. 5A-B, in a third configuration, switch matrix 16can interconnect capacitors 12 and 14 in either the first phaseconfiguration shown in FIG. 3A or the second phase configuration shownin FIG. 3B. This third configuration can be referred to herein as the “⅔mode” because operation in this mode is intended to result in an outputvoltage signal at output node 26 having a voltage level that isnominally about two-thirds of the battery voltage.

As shown in FIG. 5A, in the first phase configuration of the ⅔ mode,switches 42, 46, 48, 52 and 56 are open, and switches 40, 44, 50 and 54are closed. The combination of the closed states of switches 40 and 44couples capacitor 12 between the battery voltage and output node 26. Thecombination of the closed states of switches 50 and 54 similarly couplescapacitor 14 between the battery voltage and output node 26 (i.e., inparallel with capacitor 12). Thus, in the first phase configuration ofthe ⅔ mode, the capacitor circuit defined by capacitors 12 and 14 inparallel with each other charges with respect to output node 26.

As shown in FIG. 5B, in the second phase configuration of the ⅔ mode,switches 40, 44, 46, 50, 52 and 54 are open, and switches 42, 48 and 56are closed. The combination of the closed states of switches 42, 48 and56 couples capacitors 12 and 14 in series between ground and output node26. Thus, in the second phase configuration of the ⅔ mode, the capacitorcircuit defined by capacitors 12 and 14 in series with each otherdischarges with respect to output node 26.

As illustrated in FIG. 6, comparator circuit 18 includes fourcomparators 58, 60, 62 and 64 and a voltage level generator comprisingfour resistors 66, 68, 70 and 72. Resistors 66-72 are connected inseries with each other between the battery voltage and ground. Thevalues of resistors 66-72 are selected so that the voltage at a node 74at a first input of comparator 60 (e.g., the inverting input) is ⅔(V_BATT), the voltage at a node 76 at a first input of comparator 62 is½ (V_BATT), and the voltage at a node 78 at a first input of comparator64 is ⅓ (V_BATT). The second input (e.g., the non-inverting input) ofeach of comparators 60, 62 and 64 is connected to the output voltagesignal (V_OUT). Thus, the output of comparator 60 (V_23) being highindicates that the output voltage exceeds (i.e., is greater in magnitudethan) ⅔ (V_BATT); the output of comparator 62 (V_12) being highindicates that the output voltage exceeds ½ (V_BATT); and the output ofcomparator 64 (V_13) being high indicates that the output voltageexceeds ⅓ (V_BATT). One input of comparator 58 (e.g., the invertinginput) is similarly connected to the output voltage signal. However, theother input of comparator 58 (e.g., the non-inverting input) isconnected to the reference voltage signal (V_REF). Thus, the output ofcomparator 58 (V_UD) being high indicates that the reference voltageexceeds the output voltage. Conversely, the output of comparator 58being low indicates that the output voltage exceeds the referencevoltage. The output of comparator 58 (V_UD) serves as a directioncomparison signal, indicating to control logic 20 (FIG. 1) in whichdirection, “up” or “down,” control logic 20 should cause the outputvoltage signal to change.

In the exemplary embodiment, mode selection logic 32 of control logic 20(FIG. 1) can include combinational logic that determines the mode towhich control logic 20 is to cause switch matrix 16 to switch in orderto cause the output voltage signal to change in the direction indicatedby the direction comparison signal. Mode selection logic 32 receivescomparison signals 30, comprising the outputs of comparators 58-64.Comparison signals 30 can be provided as inputs to the combinationallogic. The combinational logic can be provided in any suitable form,such as a network of logic gates (not shown). For purposes of clarity,the combinational logic is represented herein in the form of the table80 shown in FIG. 7. Nevertheless, persons skilled in the art are readilycapable of providing the logic of table 80 as a network of logic gatesor any other suitable form. Mode selection logic 32 outputs modeselection signals 36 (FIG. 1) in response to comparison signals 30 andthe combinational logic.

Table 80 indicates the “next mode” to which control logic 20 is to causeswitch matrix 16 to switch in response to a combination of the outputsof comparators 58-64 (V_UD, V_23, V_12 and V_13, respectively). Themodes indicated in table 80 are those described above: the ⅓ mode, the½A mode, the ½B mode, and the ⅔ mode. Table 80 also indicates whether to“hold” the current mode, i.e., to maintain the current mode as the nextmode. Specifically, the outputs of all of comparators 58-64 being lowindicates that the current mode is to be held in the (second phaseconfiguration of the) ⅓ mode. In all other instances, table 80 indicatesthat the mode is to switch. As described below, the mode can switch fromthe current mode to the next mode on every other clock cycle. It shouldbe noted that a reference herein to “switching” or “changing” modes orto providing a mode control signal is intended to encompass within itsscope of meaning not only changing to a different mode but also tomaintaining the same mode at the time during which mode switching canoccur, i.e., switching or changing from the current mode to the “next”mode in an instance in which both the current mode and next mode are thesame. Also note that in the exemplary embodiment table 80 omits theinstance in which the outputs of all of comparators 58-64 are high, asthis combination would indicate that control logic 20 is to cause theoutput voltage signal to approach the battery voltage, which may beundesirable. Nevertheless, in other embodiments such an output andassociated additional mode can be provided.

Although not shown for purposes of clarity, mode selection logic 32(FIG. 1) can include not only the logic reflected in table 80 but alsoencoding logic to encode some or all of the output, i.e., the next mode,and provide mode selection signals 36 in an encoded form. The encodinglogic can encode the output in the form of, for example, a 3-bit word(MODE[2:0]). For example, the next mode output “⅓″ can be encoded as“001”; the next mode output “½A” can be encoded as “010”; the next modeoutput “½B” can be encoded as “011”; and the next mode output “⅔″ can beencoded as “100”. As providing such encoding logic is well within thecapabilities of persons skilled in the art, it is not shown or describedin further detail herein.

As illustrated in FIG. 8, switch control logic 34 can receive modeselection signals 36, which may be in the above-described encoded formof a 3-bit word (MODE[2:0]) and the “hold” signal. Note that theMODE[2:0] word and “hold” signal together indicate the next mode towhich control logic 20 is to switch. The “hold” signal can be latchedinto a flip-flop 82 in control logic 34. The MODE[2] bit can be latchedinto a flip-flop 84 in control logic 34. The MODE[1] bit can be latchedinto a flip-flop 86 in control logic 34. The MODE[0] bit can be latchedinto a flip-flop 88 in control logic 34. Flip-flops 82-88 can betriggered, i.e., caused to latch their inputs, on every other cycle ofthe clock signal (CLOCK). Another flip-flop 90 can divide the clocksignal by two and provide the divided clock signal to the clock inputsof flip-flops 82-88.

Switch control logic 34 also includes decoder logic 92 coupled to theoutputs of flip-flops 82-88. Decoder logic 92 decodes the latchedMODE[2:0] word and “hold” signal into the individual switch controlsignals 38 (S1-S9) that control the above-described switches 40-56 ofswitch matrix 16. Note that while mode selection signals 36 indicate the“next” mode, the latched MODE[2:0] word and “hold” signal indicate the“current” mode. Decoder logic 92 produces switch control signals 38(S1-S9) in response to the current mode and the clock signal.

The operation of decoder logic 92 is reflected in the circuit diagramsof FIGS. 2-5. Note that for each mode configuration, switches 40-56 inFIGS. 2-5 assume the first phase configuration during one half of eachclock cycle and assume the second phase configuration during the otherhalf of each clock cycle. In response to the latched MODE[2:0] wordindicating the ⅓ mode or “001,” decoder logic 92 produces switch controlsignals 38 (S1-S9) to set switches 40-56 to the states shown in FIG. 2Aduring the first half of each clock cycle and to the states shown inFIG. 2B during the second half of each clock cycle. In response to thelatched MODE[2:0] word indicating the ½A mode or “010,” decoder logic 92produces switch control signals 38 (S1-S9) to set switches 40-56 to thestates shown in FIG. 3A during the first half of each clock cycle and tothe states shown in FIG. 3B during the second half of each clock cycle.In response to the latched MODE[2:0] word indicating the ½B mode or“011,” decoder logic 92 produces switch control signals 38 (S1-S9) toset switches 40-56 to the states shown in FIG. 4A during the first halfof each clock cycle and to the states shown in FIG. 4B during the secondhalf of each clock cycle. In response to the latched MODE[2:0] wordindicating the ⅔ mode or “100,” decoder logic 92 produces switch controlsignals 38 (S1-S9) to set switches 40-56 to the states shown in FIG. 5Aduring the first half of each clock cycle and to the states shown inFIG. 5B during the second half of each clock cycle. In response to thelatched “hold” signal indicating the “hold” mode, decoder logic 92produces switch control signals 38 (S1-89) to maintain switches 40-56 intheir previous mode configurations during each half of the next clockcycle.

An example of the operation of voltage converter 10 in the exemplaryembodiment is shown in FIG. 9. Although not shown for purposes ofclarity, the output voltage (V_OUT) begins at an initial level of zerovolts or ground (GND). In the illustrated example, a reference voltage(V_REF) is input. Initially, i.e., before timepoint 94, V_REF has avoltage that is between a level of one-half the battery voltage (½(V_BATT) and two-thirds of the battery voltage (⅔ (V_BATT). Initially,the combination of the states of comparison signals 30 (V_UD, V_13, V_12and V23) corresponds to the ⅓ mode, because V_OUT is less than one-thirdof the battery voltage (⅓ (V_BATT). Thus, mode selection signals 36(FIG. 1) indicate that the next mode is the ⅓ mode. In the ⅓ mode, theoperation of the capacitor circuit causes V_OUT to begin rising toward alevel of ⅓ (V_BATT). It should be noted that the frequency of the clocksignal (CLOCK) shown in FIG. 9 is intended only to be exemplary and canbe higher in other embodiments. As the clock signal shown in FIG. 9 isshown for purposes of clarity as having a relatively low frequency, thesmall variations in V_OUT corresponding to the charging and dischargingof the capacitor circuit as it is switched by switch matrix 16 on everyone-half clock cycle are not apparent in FIG. 9.

At timepoint 94, V_OUT reaches a level of ⅓ (V_BATT). In response, thecombination of the states of comparison signals 30 (V_UD, V_13, V_12 andV23) changes to correspond to the ½A mode, because V_OUT exceeds ⅓(V_BATT) but is less than ½ (V_BATT). Note that the current mode oroutput of decoder logic 92 (FIG. 8) changes on every other clock cycleand latches the value of the next mode. In the ½A mode, the operation ofthe capacitor circuit causes V_OUT to continue rising toward a level of½ V_BATT.

At timepoint 96 in this example, V_OUT reaches a level of ½ (V_BATT). Inresponse, the combination of the states of comparison signals 30 (V_UD,V_13, V_12 and V23) changes to correspond to the ⅔ mode, because V_OUTexceeds ½ (V_BATT) but is less than ⅔ (V_BATT). In the ⅔ mode, theoperation of the capacitor circuit causes V_OUT to continue risingtoward a level of ⅔ V_BATT. However, at timepoint 98 V_OUT reachesV_REF. In response, the combination of the states of comparison signals30 (V_UD, V_13, V_12 and V23) changes to correspond to the ½B mode. Inthe ½B mode, the operation of the capacitor circuit causes V_OUT to falltoward a level of ½ (V_BATT). However, at timepoint 100 V_OUT crossesV_REF again. In response, the combination of the states of comparisonsignals 30 (V_UD, V_13, V_12 and V23) changes to correspond to the ⅔mode, and V_OUT again begins rising toward a level of ⅔ (V_BATT) attimepoint 103. Thus, once V_OUT reaches V_REF, V_OUT alternately crossesV_REF as it rises toward the ⅔ mode configuration and crosses V_REF asit falls toward the ½B mode configuration. Between timepoints 98 and102, on average, V_OUT is maintained at a voltage approximately equal toV_REF. The variations or deviations in V_OUT from V_REF can be minimizedby including filter circuitry at the output of voltage converter 10,such as capacitor 28 (FIG. 1).

In the example shown in FIG. 9, at timepoint 104 V_REF is changed to anew level between ⅓ (V_BATT) and ½ (V_BATT). In response, thecombination of the states of comparison signals 30 (V_UD, V_13, V_12 andV23) changes to correspond to the ⅓ mode. In the ⅓ mode, the operationof the capacitor circuit causes V_OUT to fall toward a level of ⅓(V_BATT). However, at timepoint 106 V_OUT reaches V_REF. In response,the combination of the states of comparison signals 30 (V_UD, V_13, V_12and V23) changes to correspond to the ½A mode. In the ½A mode, theoperation of the capacitor circuit causes V_OUT to rise toward a levelof ½ (V_BATT). However, at timepoint 108 V_OUT crosses V_REF again. Inresponse, the combination of the states of comparison signals 30 (V_UD,V_13, V_12 and V23) changes to correspond to the ⅓ mode, and V_OUT againbegins falling toward a level of ⅓ (V_BATT). Thus, once V_OUT reachesthe new V_REF level, V_OUT alternately crosses V_REF as it rises towardthe ½ mode configuration and crosses V_REF as it falls toward the ⅓ modeconfiguration. After approximately timepoint 106, on average, V_OUT ismaintained at a voltage approximately equal to the new V_REF.

As illustrated in FIG. 10, the method described above with regard to theexample shown in FIG. 9 can be generalized or summarized as follows. Asindicated by blocks 110 and 112, in any of the above-described modeconfigurations (i.e., ⅓ mode, ½A mode, ½B mode and ⅔ mode), switchmatrix 16 (FIG. 1) continuously switches the capacitor circuit betweenthe first phase configuration and the second phase configuration of thatmode. This phase switching occurs in response to the clock signal, withthe first phase configuration occurring during one half of each clockcycle, and the second phase configuration occurring during the otherhalf of each clock cycle. This phase switching occurs in parallel withmode switching. As indicated by blocks 114 and 116, comparator circuit18 (FIG. 1) compares the output voltage signal (V_OUT) with thereference signal (V_REF) and produces comparison signals 30. Thecomparison signals include a direction comparison signal that indicateswhich of the output voltage signal and reference voltage signal isgreater in magnitude than the other. Control logic 20 switches the modeto a mode that corresponds to a higher output voltage if V_OUT is lessthan V_REF, as indicated by block 118. Control logic 20 switches themode to a mode that corresponds to a lower output voltage if V_OUT isgreater than V_REF, as indicated by block 120. In the exemplaryembodiment, there are essentially three modes that have levels that arefixed relative to the battery voltage: ⅓ mode, in which V_OUT is driventoward a voltage level that is one-third of the battery voltage; ½ mode,in which V_OUT is driven toward a voltage level that is one-half of thebattery voltage; and ⅔ mode, in which V_OUT is driven toward a voltagelevel that is two-thirds of the battery voltage. By switching betweentwo of these modes, control logic 20 can cause V_OUT to assume anaverage value that is approximately equal to V_REF in an instance inwhich V_REF lies between voltages corresponding to the two modes.Although in the exemplary embodiment there are three modes, in otherembodiments there can be more or fewer modes. Similarly, although in theexemplary embodiment there is no mode in which V_OUT is driven towardthe battery voltage and no mode in which V_OUT is driven toward ground,in other embodiments such modes can be included.

While various embodiments of the invention have been described, it willbe apparent to those of ordinary skill in the art that many moreembodiments and implementations are possible that are within the scopeof this invention. Accordingly, the invention is not to be restrictedexcept in light of the following claims.

1. A voltage converter, comprising: a switch matrix having a pluralityof mode configurations, each mode configuration corresponding to one ofa plurality of output signal voltages, the mode configuration beingselectable in response to a mode control signal; comparator logicimplemented to compare the output signal with a reference signal andproduce a direction comparison signal; and control logic implemented toproduce the mode control signal in response to the direction comparisonsignal.
 2. The voltage converter of claim 1, wherein each modeconfiguration is defined by a capacitor circuit having a plurality ofcapacitors interconnected with each other between a voltage potentialand an output node.
 3. The voltage converter of claim 2, wherein eachmode configuration has a first phase configuration in which thecapacitor circuit is charged and a second phase configuration in whichthe capacitor circuit is discharged.
 4. The voltage converter of claim3, wherein the switch matrix switches between the first phaseconfiguration and the second phase configuration of a selected modeconfiguration in response to a clock signal to produce an output signalat the output node having an output signal voltage corresponding to theselected mode configuration.
 5. The voltage converter of claim 1,wherein the direction comparison signal indicates which of the outputsignal and the reference signal is greater.
 6. The voltage converter ofclaim 5, wherein the control logic produces the mode control signal toselect a mode configuration corresponding to an output signal voltagegreater than the reference signal in response to the directioncomparison signal indicating that the reference signal is greater thanthe output signal, and the control logic produces the mode controlsignal to select a mode configuration corresponding to an output signalvoltage less than the reference signal in response to the directioncomparison signal indicating that the output signal is greater than thereference signal.
 7. The voltage converter of claim 1, wherein theswitch matrix has three mode configurations.
 8. The voltage converter ofclaim 7, wherein the three mode configurations include a first modeconfiguration corresponding to an output signal voltage of one-third ofa base reference voltage, a second mode configuration corresponding toan output signal voltage of one-half of the base reference voltage, anda third mode configuration corresponding to an output signal voltage oftwo-thirds of the base reference voltage.
 9. The voltage converter ofclaim 8, wherein the comparator logic includes a plurality ofcomparators and a voltage level generator circuit that generates aplurality of reference voltage levels and provides a selected referencevoltage level to a first input of each comparator, each voltage levelcorresponding to one of the plurality of output signal voltages, thesecond input of each comparator coupled to the output signal, eachcomparator providing a corresponding comparison signal.
 10. The voltageconverter of claim 9, wherein the plurality of comparators comprisesthree comparators.
 11. The voltage converter of claim 10, wherein afirst comparator compares the output signal with a first referencevoltage signal having a voltage of a first fraction of a base referencevoltage and produces a first comparison signal.
 12. The voltageconverter of claim 11, wherein the first comparison signal indicateswhether the output signal voltage exceeds the first fraction of the basereference voltage.
 13. The voltage converter of claim 11, wherein asecond comparator compares the output signal with a second referencevoltage signal having a voltage of a second fraction of a base referencevoltage greater than the first fraction of the base reference voltageand produces a second comparison signal.
 14. The voltage converter ofclaim 13, wherein the second comparison signal indicates whether theoutput signal voltage exceeds the second fraction of the base referencevoltage.
 15. The voltage converter of claim 13, wherein a thirdcomparator compares the output signal with a third reference voltagehaving a voltage of a third fraction of a base reference voltage greaterthan the second fraction of the base reference voltage signal andproduces a third comparison signal.
 16. The voltage converter of claim15, wherein the third comparison signal indicates whether the outputsignal voltage exceeds the third fraction of the base reference voltage.17. The voltage converter of claim 15, wherein the three modeconfigurations include a first mode configuration corresponding to anoutput signal voltage of the first fraction of the base referencevoltage, a second mode configuration corresponding to an output signalvoltage of the second fraction of the reference voltage, and a thirdmode configuration corresponding to an output signal voltage of thethird fraction of the reference voltage.
 18. The voltage converter ofclaim 17, wherein the first fraction is one-third, the second fractionis one-half and the third fraction is two-thirds.
 19. The voltageconverter of claim 17, wherein the control logic comprises combinationallogic responsive to combinations of the first, second and thirdcomparison signals.
 20. The voltage converter of claim 19, wherein thecombinational logic produces the mode control signal to select a modeconfiguration corresponding to an output signal voltage of the firstfraction of the base reference voltage if the first comparison signalindicates that the output signal voltage does not exceed the firstfraction of the base reference voltage and the direction comparisonsignal indicates that the reference signal is greater than the outputsignal.
 21. The voltage converter of claim 19, wherein the combinationallogic produces the mode control signal to select a mode configurationcorresponding to an output signal voltage of the first fraction of thebase reference voltage if the first comparison signal indicates that theoutput signal voltage exceeds the first fraction of the base referencevoltage, the second comparison signal indicates that the output voltagedoes not exceed the second fraction of the base reference voltage, andthe direction comparison signal indicates that the reference signal isless than the output signal.
 22. The voltage converter of claim 19,wherein the combinational logic produces the mode control signal toselect a mode configuration corresponding to an output signal voltage ofthe second fraction of the base reference voltage if the firstcomparison signal indicates that the output signal voltage exceeds thefirst fraction of the base reference voltage, the second comparisonsignal indicates that the output voltage does not exceed the secondfraction of the base reference voltage, and the direction comparisonsignal indicates that the reference signal is greater than the outputsignal.
 23. The voltage converter of claim 19, wherein the combinationallogic produces the mode control signal to select a mode configurationcorresponding to an output signal voltage of the second fraction of thebase reference voltage if the second comparison signal indicates thatthe output voltage exceeds the second fraction of the base referencevoltage, the third comparison signal indicates that the output voltagedoes not exceed the third fraction of the base reference voltage, andthe direction comparison signal indicates that the reference signal isless than the output signal.
 24. The voltage converter of claim 19,wherein the combinational logic produces the mode control signal toselect a mode configuration corresponding to an output signal voltage ofthe third fraction of the base reference voltage if the secondcomparison signal indicates that the output voltage exceeds the secondfraction of the base reference voltage, the third comparison signalindicates that the output voltage does not exceed the third fraction ofthe base reference voltage, and the direction comparison signalindicates that the reference signal is greater than the output signal.25. The voltage converter of claim 19, wherein the combinational logicproduces the mode control signal to select a mode configurationcorresponding to an output signal voltage of the third fraction of thebase reference voltage if the third comparison signal indicates that theoutput voltage exceeds the third fraction of the base reference voltageand the direction comparison signal indicates that the reference signalis less than the output signal.